The amount of data transmission as well as transmission rate of the data in communications between a DRAM(dynamic random access memory) and a CPU(central processing unit) or between digital chips such as ASICs(application specific integrated circuits) continue to rise.
However, in such communications, the data transmission rate is limited by time jitter occurring in a PLL(phase locked loop)/DLL(delay locked loop) circuit, an offset due to dimensional deviations in the process of producing transmitters and receivers and so on. Also a setup/hold time of a receiver circuit is not long enough, due to a reduction in a data size margin and a time margin resulting from an inter-symbol interference (ISI) between signals. In such a case, the ISI is generated due to attenuation in high frequency components of signals in a transmission channel. Moreover, a time skew is generated, due to a difference in time required for transmitting a signal through a channel, between signals or between a clock and the signal.
In the meantime, in order to transmit a signal at a high speed by overcoming a bandwidth limitation given in transmission channels of a bus structure where a plurality of chips are interconnected through one conductive line, technologies for amplifying a high-frequency component of a signal in a transmitter or in a receiver have been developed.
The conventional technology for amplifying a high-frequency component of a signal in the transmitter is referred to as a pre-emphasis scheme, a structure thereof being shown in FIG. 1. As shown in FIG. 1, the operation of the transmitter can be represented asH(z)=1−a·z−1,so that it can serve as a high pass filter(HPF), wherein ‘a’ represents a constant and ‘z’ means a variable complex number. The pre-emphasis scheme has usually been applied to current mode signaling circuits. However, since a SSTL (series stub terminated logic) channel for a DRAM interface employs a full-swing voltage-mode driving technique at a transmitter output, it is difficult to use the pre-emphasis scheme for the SSTL channel.
The conventional technologies for amplifying a high-frequency component of a signal in the receiver are indicated in FIGS. 2 and 3. The operation of the receiver in FIG. 2, i.e, a linear feed-forward scheme, can be represented byH(z)=1−a·z−1,wherein ‘a’ represents a constant and ‘z’ means a variable complex number. In the linear feed-forward scheme, a capacitor is required to store an input analog signal. In this way, noise immunity of the receiver may be degraded due to the analog nature of the signal and an equalization circuit cannot be simplified due to the presence of analog storage circuits, e.g., capacitors.
Meanwhile, the operation of the receiver in FIG. 3, which is called as a decision feedback equalization(DFE) scheme, can be represented byY[n]=x[n]−a·Ŷ[n−1],wherein ‘n’ is a positive integer, x[n] represents a current external data signal fed to an equalizing amplifier, Ŷ[n−1] indicates a preceding decision result, ‘a’ means a constant and Y[n] shows an output voltage of the equalizing amplifier. In the DFE scheme, after it is determined whether a preceding external data signal x[n−1] is H(High) or L(Low), a fraction of the preceding decision result, a·Ŷ[n−1], is fed back to amplify a high-frequency component of the current external data signal. In contrast to the above-mentioned linear analog feed-forward scheme, high noise immunity is achieved in the DFE scheme because of the digital nature of the feedback signal a·Ŷ[n−1] and an equalization circuit employing the DFE scheme may be much simplified owing to the absence of analog storage circuits.
However, the DFE scheme has a limitation in a high-speed transmission due to a delay time at its feedback path. Furthermore, due to a difference in time required for transmitting signals through channels, there is a time skew between transmitted signals or between a clock and a transmitted signal. The skew has an adverse effect on signal transmission at a high speed. For the normal operation of an input circuit in a receiver, a setup/hold time should be sufficient as needed, but the time skew makes it difficult.
To solve the above-mentioned problems in the DFE scheme, the determination of suitable timing of a clock is required. For example, in the prior art, a proper sampling time is attained by over-sampling a transmitted signal (i.e., data are sampled twice or more per one period of the signal) for each data pin of a receiver. That is, in a 2× over-sampling scheme as shown in FIG. 4, the data of the signal are sampled three times in two periods of the signal, and if first two samples have a same value, the delay in the sampling clock may increase. On the other hand, if last two samples have a same value, the delay time of the sampling clock can be reduced. Through such a feedback procedure, a clock with a suitable delay (the timing of a sampling clock is determined to be in the middle of a specific portion of a stream of the data) is provided for each pin of the receiver.
In determining the suitable timing of a clock by using the 2× over-sampling scheme, a signal with minimal attenuation in time scale should be used. That is, if a high-frequency component of the signal is considerably attenuated while passing through a transmission channel, the time uncertainty region of data is broadened, and the scheme for determining the suitability of the clock by using the over-sampling becomes ineffective due to an increase in time jitter. Thus, the 2× over-sampling scheme cannot be used in a channel where a high-frequency component of a signal is seriously attenuated.
In transmitting a signal in the above-mentioned digital system, therefore, there may occur various problems as further explained below.
First, when a signal is transmitted at a high speed in a channel of the digital system, a high frequency component of the signal may be attenuated. Such a phenomenon causes an ISI between signals and reduces a time margin and a voltage margin of the signal, thereby making it difficult to carry out data transmission at a high speed.
Secondly, in the prior art, in order to avoid such a phenomenon, an equalizing technology is applied to either a terminal of a transmitter or that of a receiver, so that the attenuated component is compensated. However, the equalizing technology applied to the terminal of the transmitter is not applicable to a DRAM or an ASIC where a voltage at the terminal of the transmitter has a waveform of a full swing. Further, the equalizing technology applied to the terminal of the receiver has drawbacks such as low noise immunity and low-speed of data transmission.
Thirdly, when a clock signal is transmitted with a data signal from a transmitter to a receiver, a time skew is generated due to a difference in the delay time required for signals to pass through a transmission channel, which may in turn reduce the time margin of the data signal.
Fourthly, in order to solve the time skew problem, an over-sampling scheme is employed to find a suitable clock timing. However, in the occurrence of an attenuation of a signal, it is very difficult to apply such a scheme to a broadened time uncertainty region of the data signal.